80mhz 8阶带通/spl Delta//spl Sigma/-调制器,SNDR为75 dB,适用于IS-95

T. Salo, S. Lindfors, K. Halonen
{"title":"80mhz 8阶带通/spl Delta//spl Sigma/-调制器,SNDR为75 dB,适用于IS-95","authors":"T. Salo, S. Lindfors, K. Halonen","doi":"10.1109/CICC.2002.1012793","DOIUrl":null,"url":null,"abstract":"A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An 80 MHz 8th-order bandpass /spl Delta//spl Sigma/-modulator with a 75 dB SNDR for IS-95\",\"authors\":\"T. Salo, S. Lindfors, K. Halonen\",\"doi\":\"10.1109/CICC.2002.1012793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2

摘要

提出了一种全差分8阶级联带通/spl δ //spl σ /调制器。该电路仅使用两个运放大器实现,采样频率为80mhz。该电路可用于中频接收机,通过直接将输入信号从60 MHz的中频采样到20 MHz的数字中频,将频率下变频与模数转换相结合。测量峰值SNDR 75 dB 1.25 MHz带宽(- 95)。该电路采用0.35 /spl mu/m CMOS技术实现,从3.0 V电源消耗37 mW。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An 80 MHz 8th-order bandpass /spl Delta//spl Sigma/-modulator with a 75 dB SNDR for IS-95
A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信