{"title":"80mhz 8阶带通/spl Delta//spl Sigma/-调制器,SNDR为75 dB,适用于IS-95","authors":"T. Salo, S. Lindfors, K. Halonen","doi":"10.1109/CICC.2002.1012793","DOIUrl":null,"url":null,"abstract":"A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.","PeriodicalId":209025,"journal":{"name":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2002-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"An 80 MHz 8th-order bandpass /spl Delta//spl Sigma/-modulator with a 75 dB SNDR for IS-95\",\"authors\":\"T. Salo, S. Lindfors, K. Halonen\",\"doi\":\"10.1109/CICC.2002.1012793\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.\",\"PeriodicalId\":209025,\"journal\":{\"name\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2002-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2002.1012793\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2002.1012793","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
An 80 MHz 8th-order bandpass /spl Delta//spl Sigma/-modulator with a 75 dB SNDR for IS-95
A fully-differential 8th-order cascade bandpass /spl Delta//spl Sigma/-modulator is presented. The circuit is implemented using only two opamps and operates at a sampling frequency of 80 MHz. The circuit can be used in an IF-receiver to combine frequency downconversion with analog to digital conversion by directly sampling an input signal from an intermediate frequency of 60 MHz to a digital intermediate frequency of 20 MHz. The measured peak SNDR is 75 dB for a 1.25 MHz bandwidth (IS-95). The circuit is implemented with a 0.35 /spl mu/m CMOS technology and consumes 37 mW from a 3.0 V supply.