位串行VLSI接收场累加器

K. Strohbehn, A. Andreou
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引用次数: 3

摘要

讨论了一种数字位串行VLSI芯片,用于积累形成线性感受野的神经元群的神经激活。这种类型的VLSI电路是对文献中描述的最佳匹配分类器的补充。这种电路称为BFD (brute force detector)。作者在3 μm孔CMOS工艺(M83M运行)中通过MOSIS设计并制作了BFD神经元级联原型。结果表明,晶圆级、可重构版本的探测器可以构建,可以实现105个接收野的顺序。使用这种晶圆级联的接收器在雷达和声纳应用中具有很大的实用价值,对寻找地外智慧生物(SETI)也很有用。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A bit-serial VLSI receptive field accumulator
A digital bit-serial VLSI chip for accumulating neural activations of a population of neurons that form a linear receptive field is discussed. This type of VLSI circuit is complementary to the best-match classifiers described in the literature. The circuit is called a brute force detector (BFD). The authors have designed and fabricated a prototype BFD neuron cascade through MOSIS in a 3-μm p-well CMOS process (M83M run). The results indicate that a wafer-scale, restructurable version of a detector could be constructed that could implement on the order of 105 receptive fields. A receiver using a cascade of such wafers would be of great practical value for radar and sonar applications as well as useful for the search for extraterrestrial intelligence (SETI)
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