1μ m TSV过端集成对先进FinFET器件电气性能的影响

G. Hiblot, S. Van Huylenbroeck, G. van der Plas, B. de Wachter, A. Chasin, B. Kaczer, T. Chiarella, J. Mitard, Steven De Muynck, G. Beyer, E. Beyne
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引用次数: 11

摘要

在这项工作中,研究了1\ × 5μm的过孔集成对先进的体FinFET技术的影响。我们发现TSV接近的机械影响低于检测极限,但在小型设备(高天线宽高比)上观察到等离子体诱导损伤(PID)。最后,提高TSV热预算的背面退火没有增加机械冲击,尽管它部分治愈了小型设备上的PID损伤。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Impact of 1μ m TSV via-last integration on electrical performance of advanced FinFET devices
In this work, the impact of 1\times 5μm} Via-last integration on an advanced bulk FinFET technology is investigated. We find that mechanical impact of TSV proximity is below detection limit, however plasma-induced damage (PID) is observed on small devices (high antenna aspect ratio). Finally, a back-side anneal raising the TSV thermal budget shows no increase of mechanical impact though it partially cures PID damage on small devices.
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