Fully synthesized time-to-digital converter for cellular transceivers

In this paper, the design of a fully synthesizable time-to-digital converter (TDC) for digital phase locked loops including the underlying design approach is proposed. In contrast to the traditional way of full-custom implementation, the presented design flow is based on generic RTL description and VLSI tools for synthesis and automated place and route. This approach also addresses the analog and RF requirements of the TDC. Furthermore, the flow allows rapid modification and adaptation of the design with respect to distinct performance parameters. Thus, the approach enables the quick migration of designs to more advanced technology nodes. For an exemplary TDC, manufactured in 28nm, a resolution of 8.7ps was measured. This demonstrates that the proposed approach results in designs that are suitable for the use in current cellular transceivers.