EMMI Abnormal Hotspot Study for Latch up Simulation

Latch-Up is a common circuit design problem in product reliability. Because of the poor design of the integrated circuit, the P-N-P-N junction in the chip is triggered by an applied current or voltage then to happen an internal latching current. The high temperature generated by the internal latching current will burn the internal circuit or cause the circuit to work abnormally. This paper is to discuss when the IC happen latch-up, we need to prepare different test sample ex. "de-cap package sample front side sample" / "de-cap package sample back side COB (chip on board) sample"/ Blue tape COB backside sample. We also compare the difference between each test samples. Finally we discuss EMMI (Emission Microscope) hot spot experiment for latch-up simulation that needs limited of current with each different COB sample. The stress current limitation will induce EMMI result, based on this fail model and improve the product Latch-up performance by reducing parasitic BJT (bipolar transistor) circuit current gain factor ß.