SoC设计和验证的SystemC/TLM流程

2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA) Pub Date : 2015-07-30 DOI:10.1109/EAMTA.2015.7237376

M. Soto, J. A. Rodriguez, P. Fillottrani

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引用次数: 0

摘要

随着系统复杂性的增长，它们的验证成为设计流程中的瓶颈。在本文中，我们提出了一种自上而下的方法来执行从规范到寄存器传输级别(RTL)的完整流程。不同的抽象级别，例如事务级别建模(Transaction Level Modeling, TLM)，允许早期的系统验证(使用模拟或形式化方法)，减少长时间重新设计周期的风险。通过一个案例研究验证了该方法。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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SystemC/TLM flow for SoC design and verification

As systems grow in complexity, their verification becomes a bottleneck on the design flow. In this paper we propose a top-down methodology to perform the complete flow from specifications to Register Transfer Level (RTL). Different abstraction levels such as Transaction Level Modeling (TLM) allows early system verification (with simulation or formal methods), reducing the risk of long redesign cycles. The methodology is validated by showing a case study.

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2015 Argentine School of Micro-Nanoelectronics, Technology and Applications (EAMTA)

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