{"title":"一种35 ghz 20 μ m/sup /自对准PNP技术，用于超高速高密度互补双极ulsi","authors":"K. Washio, H. Shimamoto, T. Nakamura","doi":"10.1109/VLSIT.1992.200692","DOIUrl":null,"url":null,"abstract":"An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<<ETX>>","PeriodicalId":404756,"journal":{"name":"1992 Symposium on VLSI Technology Digest of Technical Papers","volume":"58 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-06-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs\",\"authors\":\"K. Washio, H. Shimamoto, T. Nakamura\",\"doi\":\"10.1109/VLSIT.1992.200692\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<<ETX>>\",\"PeriodicalId\":404756,\"journal\":{\"name\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"volume\":\"58 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-06-02\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 Symposium on VLSI Technology Digest of Technical Papers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.1992.200692\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 Symposium on VLSI Technology Digest of Technical Papers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.1992.200692","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 35-GHz 20- mu m/sup 2/ self-aligned PNP technology for ultra-high-speed high-density complementary bipolar ULSIs
An ultra-high-speed high-density self-aligned pump technology for complementary bipolar ULSIs which is fully compatible with the npn process is discussed. A low sheet-resistance p/sup +/ buried layer and an extrinsic n/sup +/ polysilicon layer with U-grooved isolation enable the transistor size to be scaled down to about 20 mu m/sup 2/. A shallow emitter junction depth of 45 nm and narrow base width of 30 nm improve maximum cutoff frequency to 35 GHz. The power dissipation of a pnp pull-down complementary emitter-follower ECL circuit for the loaded case is calculated to be reduced to 1/5 compared with the conventional ECL circuit.<>
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