{"title":"器件几何形状对高速ffv双极晶体管直流、交流和SOA的影响","authors":"R. Dutta, T. Krutsick, J. Siket","doi":"10.1109/BIPOL.2004.1365807","DOIUrl":null,"url":null,"abstract":"Detailed characterizations were performed to evaluate the influence of device geometry on the L X , AC and SOA performances of power bipolar transistors. Appropriate performance indices normalized to total device area were defmed, leading to recommendation of a novel baseemitter geometry for optimal performance. Their implementation resulted in significant reduction in silicon area for both NPN and PNP.","PeriodicalId":447762,"journal":{"name":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Influence of device geometry on DC, AC and SOA of high speed ffv bipolar transistors\",\"authors\":\"R. Dutta, T. Krutsick, J. Siket\",\"doi\":\"10.1109/BIPOL.2004.1365807\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Detailed characterizations were performed to evaluate the influence of device geometry on the L X , AC and SOA performances of power bipolar transistors. Appropriate performance indices normalized to total device area were defmed, leading to recommendation of a novel baseemitter geometry for optimal performance. Their implementation resulted in significant reduction in silicon area for both NPN and PNP.\",\"PeriodicalId\":447762,\"journal\":{\"name\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/BIPOL.2004.1365807\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Bipolar/BiCMOS Circuits and Technology, 2004. Proceedings of the 2004 Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/BIPOL.2004.1365807","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Influence of device geometry on DC, AC and SOA of high speed ffv bipolar transistors
Detailed characterizations were performed to evaluate the influence of device geometry on the L X , AC and SOA performances of power bipolar transistors. Appropriate performance indices normalized to total device area were defmed, leading to recommendation of a novel baseemitter geometry for optimal performance. Their implementation resulted in significant reduction in silicon area for both NPN and PNP.