{"title":"25gb /s单片硅光子学设计","authors":"J. Orcutt","doi":"10.1109/CSICS.2017.8240453","DOIUrl":null,"url":null,"abstract":"Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here, I examine 25 Gb/s applications in commercially available process technology with a focus on receiver sub-system optimization.","PeriodicalId":129729,"journal":{"name":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","volume":"108 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Design of monolithic silicon photonics at 25 Gb/s\",\"authors\":\"J. Orcutt\",\"doi\":\"10.1109/CSICS.2017.8240453\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here, I examine 25 Gb/s applications in commercially available process technology with a focus on receiver sub-system optimization.\",\"PeriodicalId\":129729,\"journal\":{\"name\":\"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"volume\":\"108 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CSICS.2017.8240453\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CSICS.2017.8240453","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying packaging, design and test. Here, I examine 25 Gb/s applications in commercially available process technology with a focus on receiver sub-system optimization.
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