K. Nakamura, T. Naka, Y. Kamata, T. Taguchi, T. Shimizu, Y. Ikeda, A. Nakagawa, D. Maksimović
{"title":"10A 12V 1芯片数字控制DC/DC转换器集成电路,具有高分辨率和高频DPWM","authors":"K. Nakamura, T. Naka, Y. Kamata, T. Taguchi, T. Shimizu, Y. Ikeda, A. Nakagawa, D. Maksimović","doi":"10.1109/EPEPEMC.2008.4635315","DOIUrl":null,"url":null,"abstract":"This paper introduces a 10 A 12 V single chip digitally-controlled DC/DC converter IC based on the low cost 0.6 um BiCD process. This IC includes the digital pulse width modulator (DPWM) module with the dead-time programmability. The average time resolution is 1.22 ns at the clock frequency 25 MHz on 0.6 um process. This resolution is as same as that for the counter-based DPWM with the clock frequency 817 MHz. The chip adopted low impedance metal bump technology for reducing a parasitic interconnection resistance in the power stage. The fabricated chip achieves a low on resistance 9.7 mOmega in the 20 V output LDMOS (@drain current=5 A, gate voltage=5 V). The maximum efficiency is 86.4% at output current 5 A when the input voltage, the output voltage and switching frequency and the dead-time are 12 V, 1.3 V, 780 KHz and 15 ns, respectively. The maximum voltage deviation and transient response time are 42 mV and 8 us, respectively in step-load (5 A to 10 A) transient response.","PeriodicalId":149421,"journal":{"name":"2008 13th International Power Electronics and Motion Control Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"10A 12V 1 chip digitally-controlled DC/DC converter IC with high resolution and high frequency DPWM\",\"authors\":\"K. Nakamura, T. Naka, Y. Kamata, T. Taguchi, T. Shimizu, Y. Ikeda, A. Nakagawa, D. Maksimović\",\"doi\":\"10.1109/EPEPEMC.2008.4635315\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper introduces a 10 A 12 V single chip digitally-controlled DC/DC converter IC based on the low cost 0.6 um BiCD process. This IC includes the digital pulse width modulator (DPWM) module with the dead-time programmability. The average time resolution is 1.22 ns at the clock frequency 25 MHz on 0.6 um process. This resolution is as same as that for the counter-based DPWM with the clock frequency 817 MHz. The chip adopted low impedance metal bump technology for reducing a parasitic interconnection resistance in the power stage. The fabricated chip achieves a low on resistance 9.7 mOmega in the 20 V output LDMOS (@drain current=5 A, gate voltage=5 V). The maximum efficiency is 86.4% at output current 5 A when the input voltage, the output voltage and switching frequency and the dead-time are 12 V, 1.3 V, 780 KHz and 15 ns, respectively. The maximum voltage deviation and transient response time are 42 mV and 8 us, respectively in step-load (5 A to 10 A) transient response.\",\"PeriodicalId\":149421,\"journal\":{\"name\":\"2008 13th International Power Electronics and Motion Control Conference\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-09-30\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 13th International Power Electronics and Motion Control Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EPEPEMC.2008.4635315\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 13th International Power Electronics and Motion Control Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEPEMC.2008.4635315","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
10A 12V 1 chip digitally-controlled DC/DC converter IC with high resolution and high frequency DPWM
This paper introduces a 10 A 12 V single chip digitally-controlled DC/DC converter IC based on the low cost 0.6 um BiCD process. This IC includes the digital pulse width modulator (DPWM) module with the dead-time programmability. The average time resolution is 1.22 ns at the clock frequency 25 MHz on 0.6 um process. This resolution is as same as that for the counter-based DPWM with the clock frequency 817 MHz. The chip adopted low impedance metal bump technology for reducing a parasitic interconnection resistance in the power stage. The fabricated chip achieves a low on resistance 9.7 mOmega in the 20 V output LDMOS (@drain current=5 A, gate voltage=5 V). The maximum efficiency is 86.4% at output current 5 A when the input voltage, the output voltage and switching frequency and the dead-time are 12 V, 1.3 V, 780 KHz and 15 ns, respectively. The maximum voltage deviation and transient response time are 42 mV and 8 us, respectively in step-load (5 A to 10 A) transient response.