{"title":"3.3 v 6位60 MHZ cmos双adc","authors":"F. Paillardet, P. Robert","doi":"10.1109/ICCE.1995.518034","DOIUrl":null,"url":null,"abstract":"The paper describes a 6 bit dual A/D with a 60 MHz conversion rate in a 3.3 V 0.5 /spl mu/m CMOS process. It uses autozeroed comparators combined with interpolation and offset cancellation techniques. >","PeriodicalId":306595,"journal":{"name":"Proceedings of International Conference on Consumer Electronics","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"1995-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"A 3.3 V 6 BITS 60 MHZ CMOS DUAL ADC\",\"authors\":\"F. Paillardet, P. Robert\",\"doi\":\"10.1109/ICCE.1995.518034\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper describes a 6 bit dual A/D with a 60 MHz conversion rate in a 3.3 V 0.5 /spl mu/m CMOS process. It uses autozeroed comparators combined with interpolation and offset cancellation techniques. >\",\"PeriodicalId\":306595,\"journal\":{\"name\":\"Proceedings of International Conference on Consumer Electronics\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of International Conference on Consumer Electronics\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.1995.518034\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of International Conference on Consumer Electronics","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.1995.518034","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
本文介绍了一种在3.3 V 0.5 /spl mu/m CMOS工艺下,具有60 MHz转换速率的6位双a /D器件。它使用自动归零比较器结合插值和偏移抵消技术。>
The paper describes a 6 bit dual A/D with a 60 MHz conversion rate in a 3.3 V 0.5 /spl mu/m CMOS process. It uses autozeroed comparators combined with interpolation and offset cancellation techniques. >