芯片功耗模型——系统功耗完整性分析与设计的新方法

2007 IEEE Electrical Performance of Electronic Packaging Pub Date : 2007-11-21 DOI:10.1109/EPEP.2007.4387176

E. Kulali, E. Wasserman, Ji Zheng

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引用次数: 34

摘要

为了解决全芯片电网电源完整性协同设计与优化问题，提出了一种紧凑的SPICE等效电路模型。介绍了小型芯片功率模型生成的理论和步骤。最后对芯片功耗模型的精度进行了验证。

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Chip Power Model - A New Methodology for System Power Integrity Analysis and Design

A compact SPICE equivalent circuit model of full-chip power network is proposed in this paper to address the system power integrity co-design and optimization. The theory and procedures for the generation of the compact chip power model is described. The accuracy validation of the chip power model is also presented.

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来源期刊

2007 IEEE Electrical Performance of Electronic Packaging

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