SystemC modeling of a parallel processor broadcast interconnection system

Modeling of complex hardware/software systems is becoming more difficult due to the complexity of interactions that occur between hardware and software and the need to model each component at multiple levels of detail. System modeling languages such as SystemC are assisting in this area by allowing real application level software to be interfaced with hardware models that maintain great fidelity to the actual hardware realization. This paper describes a project to develop a model of a large complex hardware/software system that is the heart of a parallel processor interconnection architecture being developed at The University of Alabama in Huntsville. The model developed allows the investigators to vary the parameters of system workload, policy for message passing protocols, and hardware features such as size of elasticity buffers and DMA controller burst size in a single homogeneous model. Initial results are encouraging and the hope is that as SystemC synthesis tools become available, the hardware components of the model can be translated automatically into hardware designs for FPGA and other rapid prototyping platforms without redesign or coding.