机载雷达并行信号处理系统的实现

Xu Junyi, Wang Xiu-tan, Peng Ying-ning
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引用次数: 0

摘要

为了完成机载雷达的杂波抑制、运动目标检测和恒定虚警率控制等实时信号处理任务,提出了一种以DSP芯片为核心处理节点的机载雷达并行信号处理系统(ARPS2)。DSP芯片采用并行架构。每个节点都有自己的私有输入和输出内存。它采用并行存储、并行处理、并行代码加载和并行数据组织等多种并行技术来实现高效率。该系统结构简单,灵活性好,易于开发。ARPS2将应用于机载雷达。它也可以应用于其他类型雷达的高速实时信号处理算法。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Realization of an airborne radar parallel signal processing system
In order to fulfil real time signal processing tasks such as clutter rejection, moving target detection (MTD) and constant false alarm rate (CFAR) control in airborne radar, an airborne radar parallel signal processing system (ARPS2) is proposed with DSP chips as its kernel processing nodes. The DSP chips are used with parallel architecture. Each node has its private input and output memory. It adopts several parallel techniques, such as parallel storage, parallel processing, parallel code loading and parallel data organization to achieve high efficiency. It has a simple structure, excellent flexibility and easiness in developing. ARPS2 is going to be applied to an airborne radar. It can also be applied to perform high-speed real time signal processing algorithms in other kinds of radar.
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