Maintaining System Signal and Power Integrity Characteristics as Part of a Module Cost-Reduction Exercise

This paper describes design activity which involved replacing an existing ceramic single chip module package design with a new organic laminate version, each using the same ASIC, for the purpose of cost reduction, and subject to stringent system level design constraints. Since the electrical properties and characteristics of the ceramic and organic package designs were not absolutely identical, it was necessary to perform electrical equivalency analyses at the system level.