宽范围频率跟踪带滑动窗口ADPLL的设计与建模

10th IEEE International NEWCAS Conference Pub Date : 2012-06-17 DOI:10.1109/NEWCAS.2012.6329008

Chuan Shan, D. Galayko, F. Anceau

{"title":"宽范围频率跟踪带滑动窗口ADPLL的设计与建模","authors":"Chuan Shan, D. Galayko, F. Anceau","doi":"10.1109/NEWCAS.2012.6329008","DOIUrl":null,"url":null,"abstract":"An architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence. A synthesizable VHDL model is created for this circuit. Simulation and syntheses results demonstrate high performance of the new architecture.","PeriodicalId":122918,"journal":{"name":"10th IEEE International NEWCAS Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Design and Modeling of ADPLL with sliding-window for wide range frequency tracking\",\"authors\":\"Chuan Shan, D. Galayko, F. Anceau\",\"doi\":\"10.1109/NEWCAS.2012.6329008\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence. A synthesizable VHDL model is created for this circuit. Simulation and syntheses results demonstrate high performance of the new architecture.\",\"PeriodicalId\":122918,\"journal\":{\"name\":\"10th IEEE International NEWCAS Conference\",\"volume\":\"31 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"10th IEEE International NEWCAS Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/NEWCAS.2012.6329008\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"10th IEEE International NEWCAS Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/NEWCAS.2012.6329008","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

提出了一种带滑动窗口的全数字锁相环(ADPLL)宽范围频率跟踪结构，以降低功耗和加快收敛速度。为该电路建立了一个可合成的VHDL模型。仿真和综合结果证明了新架构的高性能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Design and Modeling of ADPLL with sliding-window for wide range frequency tracking

An architecture of All-Digital Phase-Locked Loop (ADPLL) with sliding window for wide range frequency tracking is proposed to reduce energy consumption and to accelerate convergence. A synthesizable VHDL model is created for this circuit. Simulation and syntheses results demonstrate high performance of the new architecture.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

10th IEEE International NEWCAS Conference

自引率

0.00%

发文量