On-chip decoupling capacitor optimization technique

On-chip decoupling capacitors used for reducing power supply noise. In this paper, a design technique for sizing and placing on-chip decoupling cells based on circuits switching activity is proposed. Evaluation of this methods on Universal Serial Bus Test Chip power and USB TC with new power structure indicates that the same approach of decoupling capacitors placement in different power structure can produce up to 30 percent improvement in power supply noise level.