{"title":"1.6 kbps语音合成的低成本VLSI架构设计","authors":"Chu Yu, Hwai-Tsu Hu","doi":"10.1109/ICCE.2003.1218910","DOIUrl":null,"url":null,"abstract":"We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.","PeriodicalId":319221,"journal":{"name":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","volume":"19 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2003-06-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis\",\"authors\":\"Chu Yu, Hwai-Tsu Hu\",\"doi\":\"10.1109/ICCE.2003.1218910\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.\",\"PeriodicalId\":319221,\"journal\":{\"name\":\"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.\",\"volume\":\"19 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2003-06-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCE.2003.1218910\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2003 IEEE International Conference on Consumer Electronics, 2003. ICCE.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCE.2003.1218910","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Design of a low-cost VLSI architecture for 1.6 kbps speech synthesis
We present a low-cost architecture for speech synthesis at 1.6 kbps. The speech synthesis algorithm is formulated in terms of a hardware-oriented design. Based on our proposed speech vocoder, the novel architecture consumes lower hardware resources and is therefore suited for hardware implementation.
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