{"title":"一种高速低功耗的CMOS/SOI技术","authors":"M. Lee, M. Fujishima, K. Asada","doi":"10.1109/DRC.1993.1009569","DOIUrl":null,"url":null,"abstract":"Summary form only given. The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (t/sub m/). The measured power dissipations with 0.1- to 0.25- mu m gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15- mu m gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to t/sub m/. >","PeriodicalId":310841,"journal":{"name":"51st Annual Device Research Conference","volume":"129 7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"A high speed and low power on CMOS/SOI technology\",\"authors\":\"M. Lee, M. Fujishima, K. Asada\",\"doi\":\"10.1109/DRC.1993.1009569\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Summary form only given. The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (t/sub m/). The measured power dissipations with 0.1- to 0.25- mu m gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15- mu m gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to t/sub m/. >\",\"PeriodicalId\":310841,\"journal\":{\"name\":\"51st Annual Device Research Conference\",\"volume\":\"129 7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"51st Annual Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DRC.1993.1009569\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"51st Annual Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.1993.1009569","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Summary form only given. The propagation delay times were improved up to two times in deep-submicron CMOS/SIMOX ring oscillators by reducing the poly-Si gate thickness (t/sub m/). The measured power dissipations with 0.1- to 0.25- mu m gate length are under 1.5 fJ, while theoretical minimum power dissipations can be reduced down to 0.1 fJ for 0.15- mu m gate length at a supply voltage of 1.5 V. SOI technology shows promise for high speed and low power by reducing the gate fringing capacitance which is correlated to t/sub m/. >
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