A 1GHz 50mW dual modulus divider IC using source coupled FET logic

DUAL MODULUS BIPOLAR ECL CIRCUIT ICs have been widely used in phase locked loop (PLL) synthesizer systems. Representative applications have been in the automoble telephone or in transceivers, where low power consumption is required, because of battery operation. Accordingly, commercially available Si ECL divider ICs are not satisfactory; the lowest power consumption available is 150mW2. Gallium arsenide divider ICs, which can operate at less power consumption, are thus promising for such applications. Among the GaAs logic circuits, the Direct Coupled FET Logic (DCFL) is the most attractive for its power consumption feature. However, at present, it is questionable whether the DCFL is practical for commercial products, because of its small noise margin and process sensitivity. The GaAs Source Coupled FET Logic (SCFL)’ basic gate circuit employs a differential pair of FETs. Therefore, merely threshold voltage pairing of differentially-connected FETs is required for normal operation. Consequently, a higher chip yield can be expected.