70纳米以下微处理器电路的高性能和低功耗挑战

Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285) Pub Date : 2002-08-07 DOI:10.1109/CICC.2002.1012781

R. Krishnamurthy, A. Alvandpour, V. De, S. Borkar

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引用次数: 107

摘要

CMOS技术在70纳米节点以上的扩展变得越来越困难，这给高性能和低功耗微处理器的设计带来了新的挑战。本文讨论了所需的一些关键范式转变。本文描述了解决以下问题的电路技术:(i)增加开关和泄漏功耗，(ii)大信号缓存阵列和寄存器文件的差泄漏容限，以及(iii)全球片上互连缩放趋势恶化。

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High-performance and low-power challenges for sub-70 nm microprocessor circuits

CMOS technology scaling is becoming difficult beyond 70 nm node, raising new design challenges for high-performance and low-power microprocessors. This paper discusses some of the key paradigm shifts required. Circuit techniques to combat (i) increasing switching and leakage power dissipation, (ii) poor leakage tolerance of large-signal cache arrays and register files, and (iii) worsening global on-chip interconnect scaling trend, are described.

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Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285)

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