基于亚微米技术的最优多功能单元动态指令选择逻辑

Terrell R. Bennett, R. Sangireddy
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引用次数: 3

摘要

随着技术的发展,晶体管尺寸的减小为在减小芯片面积的情况下提高电路性能创造了许多机会。在现代大问题处理器中,动态调度逻辑的时延复杂度直接影响处理器的性能。在本文中,我们分析了亚微米技术下指令选择逻辑的时间延迟的尺度,并提出了一种新的设计,为两个类似的功能单元提供一个单一的选择树。该设计基于树形结构,使用两个和四个输入的仲裁单元,可以处理一个或两个功能单元。基于四种亚微米技术的模拟,显示了技术和设计决策的影响。当服务于单个功能单元时,从130纳米技术到45纳米技术,选择逻辑树中的延迟平均减少了60%。如图所示,双授权仲裁单元构建的树将同时为多个功能单元提供服务,与多个单授权树相比,延迟减少了65% 1。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies
As the technology scales, reduction in transistor size creates many opportunities for increased circuit capabilities in reduced chip area. In modern wide-issue processors, performance of the processor is directly impacted by the time delay complexity of the dynamic scheduling logic. In this paper, we analyze the scaling of time delay of instruction select logic at the submicron technologies, and also present novel designs that provide a single selection tree for two similar functional units. The designs are based on a tree structure using arbiter cells of two and four inputs which can handle one or two functional units. The effects of technology and design decisions are shown based on simulations using four submicron technologies. The delays in the select logic trees are shown to decrease by an average of 60% from 130 nm technology to 45 nm technology when servicing a single functional unit. The double grant arbiter cells are shown to build a tree that will serve multiple functional units simultaneously with 65% lesser delay as compared to multiple single-grant trees1.
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