{"title":"HEVC的低成本视频变换","authors":"Chieh-Yang Liu, Wen-Quan He, Yung-Ming Chang, Yuan-Ho Chen","doi":"10.1109/ICIST.2014.6920370","DOIUrl":null,"url":null,"abstract":"In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.","PeriodicalId":306383,"journal":{"name":"2014 4th IEEE International Conference on Information Science and Technology","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2014-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Low-cost video transform for HEVC\",\"authors\":\"Chieh-Yang Liu, Wen-Quan He, Yung-Ming Chang, Yuan-Ho Chen\",\"doi\":\"10.1109/ICIST.2014.6920370\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.\",\"PeriodicalId\":306383,\"journal\":{\"name\":\"2014 4th IEEE International Conference on Information Science and Technology\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2014-04-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2014 4th IEEE International Conference on Information Science and Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICIST.2014.6920370\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 4th IEEE International Conference on Information Science and Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICIST.2014.6920370","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In this paper, we present a hardware design which can support the inverse transform size from 32×32 in high efficiency video coding (HEVC) and is implemented by a using single 1-D IDCT core with a memory to low cost architecture. The proposed 1-D IDCT core employs two calculating paths to achieve a high throughput rate and is implemented by a 1-D inverse transform which can calculate 1st-D and 2nd-Ddata simultaneously in two parallel paths. The proposed 2-D transform core can implement a throughput rate of 332-Mpels/s with 129k gate area.
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