14nm铁电FinFET技术,具有陡峭的亚阈值斜率,适用于超低功耗应用

Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, S. Banna
{"title":"14nm铁电FinFET技术,具有陡峭的亚阈值斜率,适用于超低功耗应用","authors":"Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, S. Banna","doi":"10.1109/IEDM.2017.8268393","DOIUrl":null,"url":null,"abstract":"Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and Idsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.","PeriodicalId":412333,"journal":{"name":"2017 IEEE International Electron Devices Meeting (IEDM)","volume":"56 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"150","resultStr":"{\"title\":\"14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications\",\"authors\":\"Z. Krivokapic, U. Rana, R. Galatage, A. Razavieh, A. Aziz, J. Liu, J. Shi, H. Kim, R. Sporer, C. Serrao, A. Busquet, P. Polakowski, J. Müller, W. Kleemeier, A. Jacob, D. Brown, A. Knorr, R. Carter, S. Banna\",\"doi\":\"10.1109/IEDM.2017.8268393\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and Idsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.\",\"PeriodicalId\":412333,\"journal\":{\"name\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"volume\":\"56 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"150\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE International Electron Devices Meeting (IEDM)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2017.8268393\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE International Electron Devices Meeting (IEDM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2017.8268393","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 150

摘要

厚度从3到8nm的掺杂半氟铁电层被集成到最先进的14nm FinFET技术中,无需进一步的工艺修改。铁电器件显示出改善的亚阈值斜率(低至54mV/dec)和Idsat(高达165%)。C-V曲线显示出轻微的铁电滞后。我们首次证明了带有铁电器件的环形振荡器可以在与常规电介质相似的频率下工作,而改进的亚阈值斜率降低了它们的有功功率。我们还提出了一个铁电mosfet模型,该模型涵盖了负(NCFET)和正(PCFET)铁电电容(CFE)器件。通过精心设计电容匹配的铁电器件,可以在不牺牲速度的情况下显著节省功耗。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
14nm Ferroelectric FinFET technology with steep subthreshold slope for ultra low power applications
Doped hafnia ferroelectric layers with thicknesses from 3 to 8nm are integrated into state-of-the-art 14nm FinFET technology without any further process modification. Ferroelectric devices show improved subthreshold slope (as low as 54mV/dec) and Idsat (up to 165% increase). C-V curves show slight ferroelectric hysteresis. For the first time, we show that ring oscillators with ferroelectric devices can operate at frequencies similar to regular dielectrics, while improved subthreshold slope reduces their active power. We also propose a model for ferroelectric MOSFETs that spans both negative (NCFET) and positive (PCFET) ferroelectric capacitance (CFE) devices. By carefully designed capacitance matching ferroelectric devices can provide significant power savings without sacrificing the speed.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
确定
请完成安全验证×
copy
已复制链接
快去分享给好友吧!
我知道了
右上角分享
点击右上角分享
0
联系我们:info@booksci.cn Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术官方微信