On Wafer Burn-in Strategies for MCM Die

The high cost associated with replacing faulty die in many MCM technologies suggests that die used in their manufacture be known to be good with high confidence. This requires some burn-in of the die since significant "infant mortality" failures are observed for semiconductor parts. Burn-in generally involves mounting the die on temporary die carriers so that signals can be applied to activate the circuits. In this paper we present a more efficient strategy that allows the burn-in of the die on the wafer before they are diced. Our proposed approach requires that power, ground and clock connections to each die be fabricated on the wafer so that all the circuits can be powered up and clocked using only a few probe connects to the wafer. These extra connections use the space between die, and are lost once the wafer is diced into individual circuits. During burn-in, the circuits are activated in the built-in self test (BIST) mode. Here inputs to subcircuits within each die is provided by linear feedback shift registers. Power dissipation and thermal stress during burn-in is managed by controlling the air flow over the wafer surface and by appropriate selection of the thermal conduction properties of the temporary wafer carrier system employed. It is also possible to selectively power up subsets of the die to manage power dissipation. Wafer level burn-in promises to be a cost effective approach for delivering known good die.