多孔sioch薄膜衬垫下电路(CUP)结构低成本芯片封装的综合工艺设计

Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005. Pub Date : 2005-06-06 DOI:10.1109/IITC.2005.1499905

M. Tagami, H. Ohtake, M. Abe, F. Ito, T. Takeuchi, K. Ohto, T. Usami, M. Suzuki, T. Suzuki, N. Sashida, Y. Hayashi

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引用次数: 12

摘要

针对多孔SiOCH (k=2.55)/Cu双衬垫互连，提出了一种基于衬垫下电路(CUP)结构的芯片封装技术。焊盘结构是改善焊线损伤的主要途径。在成型过程中，降低成型材料的热膨胀系数(CTE)是非常重要的。将这些封装过程中的应力控制与人为的低k沉积相结合，高性能65纳米节点ULSI芯片以低成本的QFP和传统的线键合提供。

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Comprehensive process design for low-cost chip packaging with circuit-under-pad (CUP) structure in porous-SiOCH film

Chip packaging technology with a circuit-under-pad (CUP) structure is developed for porous SiOCH (k=2.55)/Cu dual-damascene interconnects. Wire bonding damage is mainly improved by the pad structure. For the molding process, it is important to decrease the coefficient of thermal expansion (CTE) of the molding compounds. Combining the stress controls in these packaging processes with the contrived low-k deposition, high performance 65 nm-node ULSI chips are furnished in low-cost QFP with conventional wire bonding.

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Proceedings of the IEEE 2005 International Interconnect Technology Conference, 2005.

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