{"title":"辐射环境下电路TMR保护的验证与优化","authors":"Ó. Ruano, J. A. Maestro, P. Reviriego","doi":"10.1109/DDECS.2011.5783120","DOIUrl":null,"url":null,"abstract":"A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.","PeriodicalId":231389,"journal":{"name":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Validation and optimization of TMR protections for circuits in radiation environments\",\"authors\":\"Ó. Ruano, J. A. Maestro, P. Reviriego\",\"doi\":\"10.1109/DDECS.2011.5783120\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.\",\"PeriodicalId\":231389,\"journal\":{\"name\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-04-13\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DDECS.2011.5783120\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DDECS.2011.5783120","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Validation and optimization of TMR protections for circuits in radiation environments
A methodology based on optimization processes and software fault injection is presented to verify and improve TMR protection against SEUs. It allows validating the reliability achieved by the protection, optimizing the solution area cost.