一种有效的SAR-ADC比较器设计方法

Tejender Singh, S. Tripathi
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引用次数: 1

摘要

在现代技术发明中,在电子部门观察到重要的增长。所有的电子设备都处理模拟或数字信号。随着CMOS技术的进步,IC被设计成可以用于电子系统,其中主要关注的是功耗而不影响设备的性能。该系统的关键模块之一是模数转换器(ADC),它是模拟世界与数字世界之间的接口。在目前流行的ADC架构中,最常用的一种是逐次逼近寄存器。基于SAR的ADC在低功耗和高速下实现了更高的采样率。它适用于数据采集,并通过提供高能量效率,在设计复杂性和功耗之间提供了有价值的权衡。在SAR-ADC体系结构中,比较器是消耗大量功率的重要模块之一。本文对比了采用90nm和45nm CMOS技术模拟的比较器设计,降低了SAR-ADC的整体功耗。最后总结出合适的方法,可以实现超低功耗,并且可以在不影响SAR-ADC性能的情况下用于所有电子植入器件。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
An Efficient Approach to Design a Comparator for SAR-ADC
In modern expertise inventions the essential growth has been observed in electronic sectors. All the electronic devices work on the signals that can be either analog or digital. With the advancement in CMOS technologies, IC’s were designed that can be used in electronic systems, where the major concern was power consumption without affecting the performance of the device. One of the vital blocks in this system is analog-digital converter (ADC) that acts as interface amid the analog worlds to the digital world. Among the prevailing ADC architectures, one of the utmost used is successive approximation register. SAR based ADC achieves an improved sampling rate at low power and high speed. It is appropriate for data acquisition and provides a worthy trade-off amongst design complexity and power dissipation by providing high-energy efficiency. In SAR-ADC architectures, one of the vital blocks that consume much amount of power is comparator. This paper converses the design of comparator simulated at 90nm and 45nm CMOS technology that has reduced the overall power consumption of SAR-ADC. Finally, it concludes the appropriate method that can be utilized to accomplish ultra-low power consumption and can be used for all electronic implant devices without affecting the performance of SAR-ADC.
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