45纳米以下全平面NAND闪存阵列的可扩展性

2009 IEEE International Memory Workshop Pub Date : 2009-05-10 DOI:10.1109/IMW.2009.5090607

P. Blomme, J. van Houdt

{"title":"45纳米以下全平面NAND闪存阵列的可扩展性","authors":"P. Blomme, J. van Houdt","doi":"10.1109/IMW.2009.5090607","DOIUrl":null,"url":null,"abstract":"We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.","PeriodicalId":113507,"journal":{"name":"2009 IEEE International Memory Workshop","volume":"93 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-05-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm\",\"authors\":\"P. Blomme, J. van Houdt\",\"doi\":\"10.1109/IMW.2009.5090607\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.\",\"PeriodicalId\":113507,\"journal\":{\"name\":\"2009 IEEE International Memory Workshop\",\"volume\":\"93 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-05-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International Memory Workshop\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IMW.2009.5090607\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International Memory Workshop","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IMW.2009.5090607","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

我们模拟了全平面NAND阵列的耦合比。我们已经证明，对于通道长度低至15nm的情况，浮栅干扰没有基本限制。缩放NAND阵列的主要限制是由于边缘场导致控制门耦合的损失，导致存储单元的编程电压大幅增加，即使使用5nm EOT IPD也是如此。

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Scalability of Fully Planar NAND Flash Memory Arrays Below 45nm

We have simulated the coupling ratios in fully planar NAND arrays. We have shown that floating gate interference is no fundamental limitation for channel lengths down to 15 nm. The main limitation for scaling NAND arrays is the loss of control gate coupling due to fringing fields, leading to a strong increase in the programming voltage of the memory cells, even when using a 5 nm EOT IPD.

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2009 IEEE International Memory Workshop

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