A. Osawa, Y. Kanemaru, N. Matsuda, T. Yoneda, H. Matsuki, Y. Usui, Y. Baba
{"title":"2.5 v驱动Nch第三代沟栅MOSFET","authors":"A. Osawa, Y. Kanemaru, N. Matsuda, T. Yoneda, H. Matsuki, Y. Usui, Y. Baba","doi":"10.1109/ISPSD.1999.764099","DOIUrl":null,"url":null,"abstract":"We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.","PeriodicalId":352185,"journal":{"name":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-05-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"2.5 V-driven Nch 3rd generation trench gate MOSFET\",\"authors\":\"A. Osawa, Y. Kanemaru, N. Matsuda, T. Yoneda, H. Matsuki, Y. Usui, Y. Baba\",\"doi\":\"10.1109/ISPSD.1999.764099\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.\",\"PeriodicalId\":352185,\"journal\":{\"name\":\"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-05-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.1999.764099\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"11th International Symposium on Power Semiconductor Devices and ICs. ISPSD'99 Proceedings (Cat. No.99CH36312)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.1999.764099","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
We developed a 3rd generation trench gate MOSFET driven by a gate voltage of 2.5 V. The on-resistance (R/sub on/) of the 3rd generation device has been reduced by 40% compared with the conventional (2nd generation) device, to the value of 12 m/spl Omega/ maximum (at V/sub GS/=2.5 V) by using certain techniques. In order to reduce the R/sub on/ value, it is necessary to thin the epitaxial layer and shrink the chip size. In order to thin the epitaxial layer, it is important to control trench depth exactly to maintain the drain-source breakdown voltage (V/sub DSS/). This is done by using a trench RIE machine with an in-situ monitoring system. For shrinkage of the chip size, a narrow trench formation process and a double trench (additional contact trench) structure are applied to the 3rd generation trench gate MOSFET. Using these new techniques, we succeeded in the development of a 3rd generation trench gate MOSFET with the lowest R/sub on/ value reported to date.