基于硅纳米晶体的MOS存储器及其陷阱对电荷存储特性的影响

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105) Pub Date : 1998-12-01 DOI:10.1109/ICSICT.1998.786434

Y. Shi, S. Gu, X. L. Yuan, Y.D. Zheng, K. Saito, H. Ishikuro, T. Hiramoto

{"title":"基于硅纳米晶体的MOS存储器及其陷阱对电荷存储特性的影响","authors":"Y. Shi, S. Gu, X. L. Yuan, Y.D. Zheng, K. Saito, H. Ishikuro, T. Hiramoto","doi":"10.1109/ICSICT.1998.786434","DOIUrl":null,"url":null,"abstract":"MOS memory device with a silicon nanocrystal based floating gate on a very narrow channel has been fabricated. Large threshold voltage shifts of up to 1V are obtained by applying a small electric field to the tunnel oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics\",\"authors\":\"Y. Shi, S. Gu, X. L. Yuan, Y.D. Zheng, K. Saito, H. Ishikuro, T. Hiramoto\",\"doi\":\"10.1109/ICSICT.1998.786434\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"MOS memory device with a silicon nanocrystal based floating gate on a very narrow channel has been fabricated. Large threshold voltage shifts of up to 1V are obtained by applying a small electric field to the tunnel oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.786434\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.786434","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 5

摘要

制备了一种基于硅纳米晶浮栅的极窄通道MOS存储器件。通过对隧道氧化物施加小电场进行写/擦除操作，可以获得高达1V的大阈值电压偏移。此外，我们还研究了通过热退火处理引入各种界面陷阱和缺陷的MOS二极管的电荷存储特性。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Silicon nano-crystals based MOS memory and effects of traps on charge storage characteristics

MOS memory device with a silicon nanocrystal based floating gate on a very narrow channel has been fabricated. Large threshold voltage shifts of up to 1V are obtained by applying a small electric field to the tunnel oxide for write/erase operation. Furthermore, charge storage characteristics have been investigated in the MOS diodes, where various interface traps and defects were introduced by thermal annealing treatment.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)

自引率

0.00%

发文量