Power aware design of an 8-bit pipelining asynchronous ANT-based CLA using data transition detection

A high speed and low-power 8-bit carry-lookahead adder (CLA) using two-phase all-N-transistor (ANT) blocks which are arranged in a PLA design style with power-aware pipelining is presented. The pull-up charging and pull-down discharging of the transistor arrays of the PLA are accelerated by inserting two feedback MOS transistors between the evaluation NMOS blocks and the outputs. The addition of two 8-bit binary numbers is executed in 2 cycles. The proposed power-aware pipelining design methodology using a simple data transition detection circuit takes advantage of shutting down the processing stages with identical inputs in two consecutive operations. Not only is it proved to be also suitable for long adders, the dynamic power consumption is drastically reduced by more than 50% at every process corner.