有效提高组合电路的可测试性

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors Pub Date : 1995-10-02 DOI:10.1109/ICCD.1995.528806

Yu Fang, A. Albicki

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引用次数: 7

摘要

提出了一种新的基于异或链结构的可测试性增强方案。该结构有效地提高了系统的可控性和可观测性。通过快速可测试性分析和抗随机模式节点源跟踪选择插入点。在ISCAS85基准电路上的实验表明，该方案是有效的。产生的硬件开销和性能损失相对较低。

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Efficient testability enhancement for combinational circuit

We propose a novel testability enhancement scheme based on XOR Chain Structure. The structure is effective for improving both controllability and observability. The insertion points are selected by fast testability analysis and random pattern resistant node source tracking. Experiments with ISCAS85 benchmark circuits show that the scheme is effective. The incurred hardware overhead and performance penalty is relatively low.

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来源期刊

Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors

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