{"title":"芯片级板和mcm的自动测试性分析","authors":"Marc Perbost, L. Lan, C. Landrault","doi":"10.1109/ATS.1997.643913","DOIUrl":null,"url":null,"abstract":"Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.","PeriodicalId":330767,"journal":{"name":"Proceedings Sixth Asian Test Symposium (ATS'97)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Automatic testability analysis of boards and MCMs at chip level\",\"authors\":\"Marc Perbost, L. Lan, C. Landrault\",\"doi\":\"10.1109/ATS.1997.643913\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.\",\"PeriodicalId\":330767,\"journal\":{\"name\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"volume\":\"72 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-11-17\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings Sixth Asian Test Symposium (ATS'97)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ATS.1997.643913\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings Sixth Asian Test Symposium (ATS'97)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ATS.1997.643913","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Automatic testability analysis of boards and MCMs at chip level
Minimising the testing costs of boards and MCMs implies to invest in testability analysis in addition to the use of testing standards (IEEE 1149). In this paper, we propose a testability analysis method for boards and MCMs designed at Dassault Electronique. The actual prototype realised according to this new methodology aims at helping testability expert.