III-V MOS技术:从平面到3D和4D

P. Ye
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引用次数: 0

摘要

最近,由于对高k/III-V接口的更好理解和显著改进,已经在亚微米通道长度(Lch)下实现了高漏极电流(Ids>1mA/μm)和高跨导(gm>1mS/μm)的III-V mosfet。然而,要实现超过14nm技术节点的III-V场效应管,一个主要挑战是如何有效地控制短通道效应(SCE)。由于沟道材料具有较高的介电常数和较低的带隙,III-V型mosfet比其Si对应物更容易受到SCE的影响。因此,将三维(3D)结构引入到深度低于100nm的III-V场效应管的制造中是必要的。在这次演讲中,我们将回顾最近发展的III-V MOS技术的材料和器件方面。我们还将报告一些新的进展,通过演示20-80 nm通道长度的III-V栅极全方位纳米线mosfet, EOT=1.2nm,最低SS=63 mV/dec。通过引入4D结构,可以进一步提高每节距总漏极电流。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
III–V MOS technology: From planar to 3D and 4D
Recently, III-V MOSFETs with high drain currents (Ids>1mA/μm) and high transconductances (gm>1mS/μm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of deep sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V MOS technology developed very recently. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec. The total drain current per pitch can be further enhanced by introducing 4D structures.
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