{"title":"模拟域50gbps QPSK接收机载波相位同步频率检测器","authors":"Rejin K. Raveendranath, N. Nambath, Shalabh Gupta","doi":"10.1109/IBP.2015.7230766","DOIUrl":null,"url":null,"abstract":"Compensating for frequency offset between transmitter and receiver lasers is a major challenge in coherent optical receivers. This necessitates the use of a carrier phase recovery and compensation circuitry at the receiver end which is capable of tracking large frequency offsets and laser linewidths. We propose a frequency detector which is capable of detecting frequency offsets from -100MHz to +100 MHz. The proposed frequency detector has been designed in 130nm BiCMOS technology. The design is verified with 50 Gbps QPSK, and 100 Gbps DP-QPSK signals using circuit simulations. A 50 Gbps low power analog domain QPSK receiver consisting of the proposed frequency detector consumes 650mW power. The receiver is capable of working with transmitter and receiver lasers having upto 200 kHz linewidth and 100MHz frequency offset between them.","PeriodicalId":236981,"journal":{"name":"2015 IEEE International Broadband and Photonics Conference (IBP)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Frequency detector for carrier phase synchronization in 50 Gbps QPSK receiver in analog domain\",\"authors\":\"Rejin K. Raveendranath, N. Nambath, Shalabh Gupta\",\"doi\":\"10.1109/IBP.2015.7230766\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Compensating for frequency offset between transmitter and receiver lasers is a major challenge in coherent optical receivers. This necessitates the use of a carrier phase recovery and compensation circuitry at the receiver end which is capable of tracking large frequency offsets and laser linewidths. We propose a frequency detector which is capable of detecting frequency offsets from -100MHz to +100 MHz. The proposed frequency detector has been designed in 130nm BiCMOS technology. The design is verified with 50 Gbps QPSK, and 100 Gbps DP-QPSK signals using circuit simulations. A 50 Gbps low power analog domain QPSK receiver consisting of the proposed frequency detector consumes 650mW power. The receiver is capable of working with transmitter and receiver lasers having upto 200 kHz linewidth and 100MHz frequency offset between them.\",\"PeriodicalId\":236981,\"journal\":{\"name\":\"2015 IEEE International Broadband and Photonics Conference (IBP)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 IEEE International Broadband and Photonics Conference (IBP)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IBP.2015.7230766\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 IEEE International Broadband and Photonics Conference (IBP)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IBP.2015.7230766","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Frequency detector for carrier phase synchronization in 50 Gbps QPSK receiver in analog domain
Compensating for frequency offset between transmitter and receiver lasers is a major challenge in coherent optical receivers. This necessitates the use of a carrier phase recovery and compensation circuitry at the receiver end which is capable of tracking large frequency offsets and laser linewidths. We propose a frequency detector which is capable of detecting frequency offsets from -100MHz to +100 MHz. The proposed frequency detector has been designed in 130nm BiCMOS technology. The design is verified with 50 Gbps QPSK, and 100 Gbps DP-QPSK signals using circuit simulations. A 50 Gbps low power analog domain QPSK receiver consisting of the proposed frequency detector consumes 650mW power. The receiver is capable of working with transmitter and receiver lasers having upto 200 kHz linewidth and 100MHz frequency offset between them.