Hysteresis behaviour of top-down fabricated ZnO nanowire transistors

Top-down Zinc Oxide (ZnO) nanowire FETs have been fabricated using conventional photolithography, ZnO atomic layer deposition (ALD) and dry etching. This paper investigates the hysteresis characteristics of these transistors at different gate bias sweep rates. Hysteresis is a measure of charge trapping and detrapping activities on the nanowire surface. Maximum hysteresis width obtained for this top-down ZnO NWFET device when measured in air was 2.2 V. This value is smaller compared to other bottom up devices which indicates better interface quality between ZnO nanowire/SiO2 interface. Subsequently, this is an important feature in order to produce reliable platform for electronic applications particularly sensing applications.