基于相对时序分析的双轨电路面积优化

13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07) Pub Date : 2007-03-12 DOI:10.1109/ASYNC.2007.10

Tiberiu Chelcea, Girish Venkataramani, S. Goldstein

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引用次数: 15

摘要

未来的深亚微米技术将以大参数变化为特征，这可能使异步设计成为大规模使用的有吸引力的解决方案。然而，异步CAD工具的投资不如同步CAD工具。即使异步工具利用了现有的同步工具流，它们也会带来很大的面积和速度开销。本文提出了几种基于时间间隔分析的启发式和最优算法，通过优化面积来改进现有的异步CAD解。优化后的电路比现有的最优算法小2.4倍，启发式算法小1.8倍。优化电路也显示出对大参数变化的弹性，产生比同步对应物更好的平均情况延迟。

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Area Optimizations for Dual-Rail Circuits Using Relative-Timing Analysis

Future deep sub-micron technologies will be characterized by large parametric variations, which could make asynchronous design an attractive solution for use on large scale. However, the investment in asynchronous CAD tools does not approach that in synchronous ones. Even when asynchronous tools leverage existing synchronous tool flows, they introduce large area and speed overheads. This paper proposes several heuristic and optimal algorithms, based on timing interval analysis, for improving existing asynchronous CAD solutions by optimizing area. The optimized circuits are 2.4 times smaller for an optimal algorithm and 1.8 times smaller for a heuristic one than the existing solutions. The optimized circuits are also shown to be resilient to large parametric variations, yielding better average-case latencies than their synchronous counterparts.

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13th IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC'07)

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