{"title":"图描述方法在超大规模集成电路结构与电学分析中的应用","authors":"Katsuyuki Ochiai, S. Tazawa, S. Nakajima","doi":"10.1109/ISSM.1994.729463","DOIUrl":null,"url":null,"abstract":"A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.","PeriodicalId":114928,"journal":{"name":"International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM","volume":"61 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Application Of A Graph Description Method For Structural And Electrical Analysis Of VLSIs\",\"authors\":\"Katsuyuki Ochiai, S. Tazawa, S. Nakajima\",\"doi\":\"10.1109/ISSM.1994.729463\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.\",\"PeriodicalId\":114928,\"journal\":{\"name\":\"International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM\",\"volume\":\"61 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISSM.1994.729463\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Symposium on Semiconductor Manufacturing, Extended Abstracts of ISSM","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISSM.1994.729463","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Application Of A Graph Description Method For Structural And Electrical Analysis Of VLSIs
A graph description method is proposed to describe layout pattern data. The Graph can express not only pattern positions but also physical attributes of the patterns. Therefore, the data processing time for structural recognition of LSI is less than a method dealing with pattern data of vertex coordinates directly.