{"title":"当我们接近0.1 /spl mu/m时,CMOS性能和密度趋势","authors":"T. Ning","doi":"10.1109/ICSICT.1998.785768","DOIUrl":null,"url":null,"abstract":"The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 /spl mu/m is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"307 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"CMOS performance and density trends as we approach 0.1 /spl mu/m\",\"authors\":\"T. Ning\",\"doi\":\"10.1109/ICSICT.1998.785768\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 /spl mu/m is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement.\",\"PeriodicalId\":286980,\"journal\":{\"name\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"volume\":\"307 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-10-21\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSICT.1998.785768\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.785768","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
CMOS performance and density trends as we approach 0.1 /spl mu/m
The technology development required to sustain the CMOS performance and density trends near and beyond 0.1 /spl mu/m is examined. It is concluded that we are fast approaching the limits of scaling conventional (bulk) CMOS. We need to look beyond scaling bulk CMOS in order to sustain the rate of CMOS performance improvement.