B类GaAs x波段功率mesfet的高压工作

S. Sriram, R. C. Clarke, R. Messham, T.J. Smith, M. Driver
{"title":"B类GaAs x波段功率mesfet的高压工作","authors":"S. Sriram, R. C. Clarke, R. Messham, T.J. Smith, M. Driver","doi":"10.1109/CORNEL.1989.79838","DOIUrl":null,"url":null,"abstract":"Surface trapping effects are shown to affect adversely the RF power performance of high-voltage GaAs MESFETs and a model is presented to explain them. It is shown that the adverse effects of surface trapping can be minimized by: (1) including an undoped layer near the surface, (2) reducing the distance between the gate and n/sup +/ ledge, and (3) making the gate recess narrower than the gate. Devices fabricated with such a structure showed excellent RF power performance at 10 GHz: P/sub 0/=678 mW/mm, G /sub A/=6.8 dB, and eta /sub PA/=51.1% at a drain-bias voltage of 12 V. The design of devices to minimize surface-trapping effects is also expected to lead to self-passivating devices that will be inherently more reliable and show less 1/f noise. The high-voltage, high-efficiency devices described here will be applicable in airborne phased array radar systems where power supply requirements and heat dissipation problems limit system performance.<<ETX>>","PeriodicalId":445524,"journal":{"name":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1989-08-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"12","resultStr":"{\"title\":\"High voltage operation in class B GaAs X-band power MESFETs\",\"authors\":\"S. Sriram, R. C. Clarke, R. Messham, T.J. Smith, M. Driver\",\"doi\":\"10.1109/CORNEL.1989.79838\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Surface trapping effects are shown to affect adversely the RF power performance of high-voltage GaAs MESFETs and a model is presented to explain them. It is shown that the adverse effects of surface trapping can be minimized by: (1) including an undoped layer near the surface, (2) reducing the distance between the gate and n/sup +/ ledge, and (3) making the gate recess narrower than the gate. Devices fabricated with such a structure showed excellent RF power performance at 10 GHz: P/sub 0/=678 mW/mm, G /sub A/=6.8 dB, and eta /sub PA/=51.1% at a drain-bias voltage of 12 V. The design of devices to minimize surface-trapping effects is also expected to lead to self-passivating devices that will be inherently more reliable and show less 1/f noise. The high-voltage, high-efficiency devices described here will be applicable in airborne phased array radar systems where power supply requirements and heat dissipation problems limit system performance.<<ETX>>\",\"PeriodicalId\":445524,\"journal\":{\"name\":\"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,\",\"volume\":\"74 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1989-08-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"12\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CORNEL.1989.79838\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings., IEEE/Cornell Conference on Advanced Concepts in High Speed Semiconductor Devices and Circuits,","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CORNEL.1989.79838","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 12

摘要

表面捕获效应对高压GaAs mesfet的射频功率性能有不利影响,并提出了一个模型来解释它们。结果表明,通过以下方法可以最大限度地减少表面捕获的不利影响:(1)在表面附近加入未掺杂层;(2)减小栅极与n/sup +/壁架之间的距离;(3)使栅极凹槽比栅极窄。在漏偏置电压为12 V时,采用该结构制备的器件在10 GHz频段表现出优异的射频功率性能:P/sub 0/=678 mW/mm, G /sub a /=6.8 dB, eta /sub PA/=51.1%。最小化表面捕获效应的器件设计也有望导致自钝化器件,其本质上更可靠,显示更少的1/f噪声。这里描述的高压、高效率器件将适用于机载相控阵雷达系统,其中电源要求和散热问题限制了系统性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
High voltage operation in class B GaAs X-band power MESFETs
Surface trapping effects are shown to affect adversely the RF power performance of high-voltage GaAs MESFETs and a model is presented to explain them. It is shown that the adverse effects of surface trapping can be minimized by: (1) including an undoped layer near the surface, (2) reducing the distance between the gate and n/sup +/ ledge, and (3) making the gate recess narrower than the gate. Devices fabricated with such a structure showed excellent RF power performance at 10 GHz: P/sub 0/=678 mW/mm, G /sub A/=6.8 dB, and eta /sub PA/=51.1% at a drain-bias voltage of 12 V. The design of devices to minimize surface-trapping effects is also expected to lead to self-passivating devices that will be inherently more reliable and show less 1/f noise. The high-voltage, high-efficiency devices described here will be applicable in airborne phased array radar systems where power supply requirements and heat dissipation problems limit system performance.<>
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