{"title":"在PWB和MCM环境下使用PPS(脉冲电源)和传统CMOS的总线传输操作的比较","authors":"T. Gabara, B. Fischer","doi":"10.1109/MCMC.1995.512014","DOIUrl":null,"url":null,"abstract":"A comparison of I/O power dissipation is compared for an adiabatic technique called PPS CMOS and conventional CMOS. The simulated results evaluated either a PWB or an MCM environment. A 32 bit bus with 8 loads on each bus is the model used for this paper. The results indicate that power and noise reductions are possible using PPS I/O buffers. Furthermore, the MCM is an optimum environment for the adiabatic logic family.","PeriodicalId":223500,"journal":{"name":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1995-01-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Comparisons of bus transfer operations using PPS (pulsed power supply) and conventional CMOS in PWB and MCM environments\",\"authors\":\"T. Gabara, B. Fischer\",\"doi\":\"10.1109/MCMC.1995.512014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A comparison of I/O power dissipation is compared for an adiabatic technique called PPS CMOS and conventional CMOS. The simulated results evaluated either a PWB or an MCM environment. A 32 bit bus with 8 loads on each bus is the model used for this paper. The results indicate that power and noise reductions are possible using PPS I/O buffers. Furthermore, the MCM is an optimum environment for the adiabatic logic family.\",\"PeriodicalId\":223500,\"journal\":{\"name\":\"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)\",\"volume\":\"194 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1995-01-31\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MCMC.1995.512014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1995 IEEE Multi-Chip Module Conference (MCMC-95)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MCMC.1995.512014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Comparisons of bus transfer operations using PPS (pulsed power supply) and conventional CMOS in PWB and MCM environments
A comparison of I/O power dissipation is compared for an adiabatic technique called PPS CMOS and conventional CMOS. The simulated results evaluated either a PWB or an MCM environment. A 32 bit bus with 8 loads on each bus is the model used for this paper. The results indicate that power and noise reductions are possible using PPS I/O buffers. Furthermore, the MCM is an optimum environment for the adiabatic logic family.