PMUT阵列与FOWLP ASIC的协同封装

D. Giusti, F. Quaglia, D. Rahul, V. S. Rao, A. Savoia, M. Shaw, D. Wee
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引用次数: 4

摘要

在医学超声扫描应用中,PMUT(压电微机械超声换能器)需要与驱动PMUT器件传输和接收反射超声信号的ASIC器件一起组装。为了产生足够高分辨率的图像,PMUT设备和配套的专用集成电路(asic)之间需要大量的互连,这是使用铜柱技术完成的。超声换能器的集成使用了传感器和ASIC晶圆之间的晶圆级键合[1]。如果非功能换能器与功能ASIC结合,则该过程会遇到产量问题,反之亦然,并且还要求ASIC模具与传感器模具具有相同的尺寸。在本文中,我们将提出一种解决方案,将已知的良好ASIC芯片组装在FOWLP(扇出晶圆级封装)中,并使用铜柱技术组装已知的良好PMUT器件,从而优化ASIC的尺寸/良率,同时仍保持所需传感器的性能。使用假模对装配流程进行了验证,以确保完全装配的FOWLP是可行的。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Co-packaging of PMUT array with FOWLP ASIC's
In medical ultrasound scanning applications PMUT (Piezo Micromachined Ultrasound transducers) need to be assembled along with the ASIC devices that drive the PMUT devices in transmission and receive the reflected ultrasound signal. To produce a sufficiently high resolution image, a large number of interconnections are required between the PMUT device and the companion ASICs (Application Specific Integrated Circuit) which is done using Cu pillar technology. This integration of Ultrasound Transducers using wafer level bonding between the traducer and the ASIC wafer has already been demonstrated [1]. This process suffers from the problem of yield if a non functioning transducer is bonded to a functioning ASIC or vice versa, and it also requires the ASIC die to be the same dimensions of the traducer die. In this article we will present a solution where known good ASIC die are assembled in a FOWLP (Fan Out wafer level Package) with known good PMUT device assembled using Cu pillar technology allowing for the optimisation of the ASIC for size/yield while still maintain the performance of the transducer required. Verification of the assembly flow has been done using a dummy die to ensure that the fully assembled FOWLP is practicable.
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