{"title":"一个使用双极四极晶体管的电可编程快速读出存储器的项目","authors":"J. Dom, P. Roux, J. Aucouturier, M. Depey","doi":"10.1109/ESSCIRC.1976.5469100","DOIUrl":null,"url":null,"abstract":"This paper presents a project on an electrically reprogrammable memory system in which the control of the avalanche degradation of the HFE of bipolar tetrode transistor is executed by the gate voltage. The design of a type REPROM with 1024 bits capacity having an access time better than 100 ns for a total power of 500 mW is attempted.","PeriodicalId":378614,"journal":{"name":"ESSCIRC 76: 2nd European Solid State Circuits Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1976-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Project on an electrically reprogrammable fast read-out memory using bipolar tetrode transistors\",\"authors\":\"J. Dom, P. Roux, J. Aucouturier, M. Depey\",\"doi\":\"10.1109/ESSCIRC.1976.5469100\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a project on an electrically reprogrammable memory system in which the control of the avalanche degradation of the HFE of bipolar tetrode transistor is executed by the gate voltage. The design of a type REPROM with 1024 bits capacity having an access time better than 100 ns for a total power of 500 mW is attempted.\",\"PeriodicalId\":378614,\"journal\":{\"name\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"volume\":\"139 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1976-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSCIRC 76: 2nd European Solid State Circuits Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSCIRC.1976.5469100\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSCIRC 76: 2nd European Solid State Circuits Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSCIRC.1976.5469100","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Project on an electrically reprogrammable fast read-out memory using bipolar tetrode transistors
This paper presents a project on an electrically reprogrammable memory system in which the control of the avalanche degradation of the HFE of bipolar tetrode transistor is executed by the gate voltage. The design of a type REPROM with 1024 bits capacity having an access time better than 100 ns for a total power of 500 mW is attempted.