A 120-Gbit/s 520-mVPP multiplexer IC using 1-µm self-aligned InP/InGaAs/InP DHBT with emitter mesa passivation ledge

We fabricated 2:1 multiplexer IC (MUX) with a retiming function by using 1−µm self-aligned InP/InGaAs/InP double heterostructure bipolar transistors (DHBTs). As a result of the high performance DHBTs and the circuit design, in which we implemented broadband impedance matching, the MUX operated at 120 Gbit/s with a power dissipation of 1.27 W and an output amplitude of 520 mV when measured on the wafer. The MUX was assembled in a module using V-connectors for practical use. In this module, the MUX operated at 113 Gbit/s with an output amplitude of 514 mW and a power dissipation of 1.4 W.