0.15 /spl mu/m n-n栅极CMOS技术的通道工程与通道外延优化和TED抑制相结合

1995 Symposium on VLSI Technology. Digest of Technical Papers Pub Date : 1995-06-06 DOI:10.1109/VLSIT.1995.520841

H. Abiko, A. Ono, R. Ueno, S. Masuoka, S. Shishiguchi, K. Nakajima, I. Sakai

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引用次数: 9

摘要

为实现实用的0.15 /spl mu/m n-n栅极CMOS技术，提出了一种结合通道外延优化和瞬态增强扩散抑制的新型通道工程。优化后的Vth波动小的信道分布提供了无反向短信道效应的nMOS和高性能的BCpMOS。

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A channel engineering combined with channel epitaxy optimization and TED suppression for 0.15 /spl mu/m n-n gate CMOS technology

A new channel engineering combined with optimization of channel epitaxy and suppression of TED (transient enhanced diffusion) is proposed for a practical 0.15 /spl mu/m n-n gate CMOS technology. An optimized channel profile with small Vth fluctuation provides an nMOS with no reverse short channel effect and a high performance BCpMOS.

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1995 Symposium on VLSI Technology. Digest of Technical Papers

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