Tunnel FET design with undoped channel and undoped drain regions: No ambipolar conduction in accumulation regime

The work highlights the benefits of one of the newly proposed TFET architecture with undoped drain. In this work the architecture has been analyzed with a stack of gate dielectric material (low-k beneath a high-k dielectric) and a heavily doped n+ pocket region between source and drain to further boost the on-state characteristics. The performance of this newly proposed architecture has been compared with symmetrically doped p-i-n DG TFET. Through simulation, the impact of varying gate bias, drain bias and metal gate work function values over the varying potential profile, energy band profile and the charge concentration profile (inside drain region of the device) has been observed and investigated carefully. Furthermore, the drain current profiles for both symmetric TFET and the TFET with undoped drain have been compared with and without pocket cases. This newly proposed architecture offers no tunneling during accumulation state and helps in reducing dynamic power dissipation through parasitic components which seems beneficial for switching applications.