{"title":"1 µm技术中温度对mos晶体管公差的影响","authors":"D. Takács, U. Schwabe, U. Burker","doi":"10.1109/IEDM.1980.189896","DOIUrl":null,"url":null,"abstract":"In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.","PeriodicalId":180541,"journal":{"name":"1980 International Electron Devices Meeting","volume":"48 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology\",\"authors\":\"D. Takács, U. Schwabe, U. Burker\",\"doi\":\"10.1109/IEDM.1980.189896\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.\",\"PeriodicalId\":180541,\"journal\":{\"name\":\"1980 International Electron Devices Meeting\",\"volume\":\"48 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1980 International Electron Devices Meeting\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.1980.189896\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1980 International Electron Devices Meeting","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.1980.189896","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
The influence of temperature on the tolerances of MOS-transistors in a 1 µm technology
In a 1 µm Si-gate technology, channel length and temperature have a strong impact on the electrical device parameters. Experimental data on the influence of the channel length and the temperature on threshold voltage, breakdown voltage and subthreshold currents are presented for different channel dopings and S/D junction depths. The results are discussed with regard to the electrical device tolerances and to limitations in standard Si-gate technologies.
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