The absolute need for physical verification and analysis of submicron circuits

The ever increasing signal speeds, finer feature sizes, greater chip sizes, lower power supply voltages, and increasing number of wiring levels dictated from now through the y e a r 2010 by the Semiconductor Industry Association (SIA) Integrated Circuit (IC) Technology Roadmap lead to ever greater interconnect signal integrity problems as time evolves. To address this issue there must be more efficient and more accurate Electronic Design Automation (EDA) tools for layout parameter extraction and timing delay and crosstalk and power simulation and analysis.