基于调节级联码的1抽头推测自适应DFE电流积分TIA RX

2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS) Pub Date : 2019-08-01 DOI:10.1109/MWSCAS.2019.8885175

A. R. Chowdhury, N. Wary, P. Mandal

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引用次数: 0

摘要

本文提出了一种基于调节级联码的电流积分TIA (RGC-CI-TIA)节能接收器。使用RGC-CI-TIA优于传统的共门(CG) CI-TIA，消除了额外的无源端接的需要，提高了电流效率，也大大降低了Rx的功率。Rx还部署了一个推测的1分路电流积分决策反馈均衡器(DFE)，它与一个2分路Tx前馈均衡器(Tx- ffe)一起补偿41“FR4 PCB走线在2.5 GHz时的18 dB损耗。通过RGC-CI-TIA提供的15的显著电压增益，所提出的Rx实现了20 mVppd的通道信号摆幅和1.2 mVppd的输入灵敏度。Rx采用180nm CMOS技术设计，数据速率为5gb /s, 1.8 V电源消耗5.25 mW，能效为1.05 pJ/bit。

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A Regulated-Cascode Based Current-Integrating TIA RX with 1-tap Speculative Adaptive DFE

In this paper, an energy efficient receiver(Rx) with a regulated-cascode based current-integrating TIA (RGC-CI-TIA) has been presented. Use of RGC-CI-TIA over conventional common-gate (CG) CI-TIA eliminates the need of additional passive termination improving the current efficiency and also results in substantial power reduction of the Rx. The Rx also deploys a speculative 1-tap current-integrating decision-feedback equalizer (DFE) which along with a 2-tap Tx feed-forward equalizer (Tx-FFE) compensate 18 dB of loss at 2.5 GHz of a 41" FR4 PCB trace. The proposed Rx achieves a channel signal-swing of 20 mVppd and input sensitivity of 1.2 mVppd by means of a significant voltage gain of 15 offered by the RGC-CI-TIA. The Rx has been designed in 180 nm CMOS technology and consumes 5.25 mW from a 1.8 V supply for a data rate of 5 Gb/s resulting in an energy efficiency of 1.05 pJ/bit.

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2019 IEEE 62nd International Midwest Symposium on Circuits and Systems (MWSCAS)

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